View MAX6889ETJ_6558096.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max6889/max6890/max6891 eeprom-config- urable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and general- purpose logic inputs and feature programmable out- puts for highly configurable power-supply sequencing applications. the max6889 features eight voltage detector inputs and ten programmable outputs. the max6890 features six voltage detector inputs and eight programmable outputs, while the max6891 features four voltage detector inputs and five programmable outputs. manual reset and margin disable inputs offer additional flexibility. all voltage detectors offer a configurable threshold for undervoltage detection. high-voltage input in1 monitors voltages from 2.5v to 13.2v in 50mv increments, or from 1.25v to 7.625v in 25mv increments. inputs in2?n7 monitor voltages from 1v to 5.5v in 20mv increments or from 0.5v to 3.05v in 10mv increments. high-voltage input in8 monitors voltages from 2.5v to 15.25v in 50mv increments, or from 1.25v to 7.625v in 25mv increments. programmable output stages control power-supply sequencing or system resets/interrupts. programmable output options include: active-high, active-low, open drain, and weak pullup. programmable timing delay blocks configure each output to wait between 25? and 1600ms before deasserting. the max6889/max6890/max6891 feature a watchdog timer for added flexibility. program the watchdog timer to assert one or more programmable outputs. the initial and normal watchdog timeout periods are indepen- dently programmable from 6.25ms to 102.4s. an smbus/i 2 c-compatible, 2-wire serial data inter- face programs and communicates with the configura- tion eeprom, the configuration registers, and the internal 512-bit user eeprom. the max6889/max6890/max6891 are available in 5mm x 5mm x 0.8mm thin qfn packages and are specified to operate over the extended temperature range (-40? to +85?). applications telecommunication/central office systems networking systems servers/workstations base stations storage equipment multi-microprocessor/voltage systems features eight (max6889), six (max6890), or four (max6891) configurable input voltage detectors high-voltage input (1.25v to 7.625v or 2.5v to 13.2v) six (max6889), five (max6890), or three (max6891) voltage inputs (0.5v to 3.05v or 1v to 5.5v) additional (max6889) high-voltage input (1.25v to 7.625v or 2.5v to 15.25v) four (max6889/max6890) or three (max6891) general-purpose logic inputs configurable watchdog timer ten (max6889), eight (max6890), or five (max6891) programmable outputs active-high, active-low, open drain, weak pullup timing delays from 25 s to 1600ms margining disable and manual reset controls 512-bit internal user eeprom endurance: 100,000 erase/write cycles data retention: 10 years i 2 c/smbus-compatible serial configuration/communication interface 1% threshold accuracy max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ________________________________________________________________ maxim integrated products 1 ordering information 19-3595; rev 1; 9/08 evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max6889 etj -40? to +85? 32 thin qfn-ep* max6890 eti -40? to +85? 28 thin qfn-ep* max6891 etp -40? to +85? 20 thin qfn-ep* smbus is a trademark of intel corp. * ep = exposed pad. pin configurations and typical operating circuit appear at end of data sheet.
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) in2?n7, v cc , sda, scl, a0, a1, gpi_ mr , margin .........................................................-0.3v to +6v in1, po_ .................................................................-0.3v to +14v in8 ..........................................................................-0.3v to +20v dbp ..........................................................................-0.3v to +3v input/output current (all pins)..........................................?0ma continuous power dissipation (t a = +70?) 20-pin thin qfn (derate 21.3mw/? above +70?)..............................................................1702mw 28-pin thin qfn (derate 21.3mw/? above +70?)..............................................................1702mw 32-pin thin qfn (derate 21.3mw/? above +70?)..............................................................1702mw operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v in1 = 6.5v to 13.2v, v in2 ? in7 = 2.7v to 5.5v, v in8 = 10v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless other- wise noted. typical values are at t a = +25?.) (notes 1, 2, 3) parameter sym b o l conditions min typ max units v in1 voltage on in1 to ensure the device is fully operational, in2?n8 = gnd 4.0 13.2 operating voltage range (note 4) voltage on any one of in2?n5 or v cc to ensure the device is fully operational, in1 = gnd 2.7 5.5 v in1 supply voltage (note 4) v in1p minimum voltage on in1 to guarantee that the device is powered through in1 6.5 v undervoltage lockout v uvlo minimum voltage on one of in2?n5 to guarantee the device is eeprom configured 2.5 v digital bypass voltage v dbp no load 2.48 2.55 2.67 v v in1 = 13.2v, in2?n8 = gnd, no load 1 1.2 ma supply current i cc writing to configuration registers or eeprom, no load 1.1 1.5 ma v in1 (50mv increments) 2.5 13.2 v in1 (25mv increments) 1.25 7.625 v in2 ? in7 (20mv increments) 1.0 5.5 v in2 ? in7 (10mv increments) 0.50 3.05 v in8 (50mv increments) 2.50 15.25 v in8 (25mv increments) 1.250 7.625 threshold voltage range v th v in2 ? in8 (high-z mode in 3.3mv increments) 0.167 1.017 v
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in1 = 6.5v to 13.2v, v in2 ? in7 = 2.7v to 5.5v, v in8 = 10v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless other- wise noted. typical values are at t a = +25?.) (notes 1, 2, 3) parameter sym b o l conditions min typ max units v in_ = 2.5v to 5.5v (20mv increments) -1 +1 % v in_ = 1v to 2.5v (20mv increments) -25 +25 mv v in_ = 1.25v to 3.05v (10mv increments) -1 +1 % t a = +25? to +85? (v in_ falling) v in_ = 0.5v to 1.25v (10mv increments) -12.5 +12.5 mv v in_ = 2.5v to 5.5v (20mv increments) -2 +2 % v in_ = 1v to 2.5v (20mv increments) -50 +50 mv v in_ = 1.25v to 3.05v (10mv increments) -2 +2 % in2?n7 threshold accuracy t a = -40? to +85? (v in_ falling) v in_ = 0.5v to 1.25v (10mv increments) -25 +25 mv v in_ = 6.25v to 13.2v (6.25v to 15.25v for in8) (50mv increments) -1 +1 % v in_ = 2.5v to 6.25v (50mv increments) -62.5 +62.5 mv v in_ = 3.125v to 7.625v (25mv increments) -1 +1 % t a = +25? to +85? (v in_ falling) v in_ = 1.25v to 3.125v (25mv increments) -31.25 +31.25 mv v in_ = 6.25v to 13.2v (6.25v to 15.25v for in8) (50mv increments) -2 +2 % v in_ = 2.5v to 6.25v (50mv increments) -125 +125 mv v in_ = 3.125v to 7.625v (25mv increments) -2 +2 % in1/in8 threshold accuracy t a = -40? to +85? (v in_ falling) v in_ = 1.25v to 3.125v (25mv increments) -62.5 +62.5 mv t a = +25? to +85? -1 +1 in_ threshold accuracy in_ = 0.6v in high-z mode (v in_ falling) t a = -40? to 85? -2 +2 % threshold hysteresis v th-hyst 0.3 % v th
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in1 = 6.5v to 13.2v, v in2 ? in7 = 2.7v to 5.5v, v in8 = 10v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless other- wise noted. typical values are at t a = +25?.) (notes 1, 2, 3) parameter sym b o l conditions min typ max units reset-threshold temperature coefficient ? v th /? 10 ppm/? threshold-voltage differential nonlinearity v th dnl -1 +1 lsb in1 input leakage current i lin1 for v in1 < the highest of v in2 ? in5 100 140 ? in2?n7 input impedance r in2 to r in7 v in1 > 6.5v 290 400 555 k ? in8 input impedance r in8 730 1000 1400 k ? in2?n8 input leakage current i lin2-lin8 in2?n8 in high-z mode, v in_ = 1.017v -50 +50 na power-up delay t pu v cc > v uvlo 3ms in_ to po_ delay t dpo v in_ falling or rising, 100mv overdrive 20 ? 000 8 25 80 s 001 1.406 1.5625 1.719 010 5.625 6.25 6.875 011 22.5 25 27.5 100 45 50 55 101 180 200 220 110 360 400 440 po_ timeout period t rp register contents (table 19) 111 1440 1600 1760 ms po_ output low v ol i sink = 4ma, output asserted 0.4 v po_ output initial pulldown current i pd v cc < v uvlo , v po = 0.8v 10 40 ? po_ output open-drain leakage current i lkg output high impedance -1 +1 ? po_ output pullup resistance r pu v po_ = 2v 6.6 10 15.0 k ? v il 0.6 mr , margin , gpi_ input voltage v ih 1.4 v mr input pulse width t mr 1s mr glitch rejection 100 ns mr to po_ delay t dmr 2s mr to dbp pullup current i mr v mr = 1.4v 5 10 15 a margin to dbp pullup current i margin v margin = 1.4v 5 10 15 a gpi_ input hysteresis 100 mv gpi_ to po_ delay t dgpi_ 200 ns gpi_ pulldown current i gpi_ v gpi_ = 0.6v 5 10 15 a watchdog input pulse width t wdi gpi_ configured as a watchdog input 50 ns
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in1 = 6.5v to 13.2v, v in2 ? in7 = 2.7v to 5.5v, v in8 = 10v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless other- wise noted. typical values are at t a = +25?.) (notes 1, 2, 3) parameter sym b o l conditions min typ max units 000 5.625 6.25 6.875 001 22.5 25 27.5 010 90 100 110 011 360 400 440 ms 100 1.44 1.60 1.76 101 5.76 6.40 7.04 110 23.04 25.60 28.16 watchdog timeout period t wd register contents (table 21) 111 92.16 102.40 112.64 s serial interface logic (sda, scl, a0, a1) logic-input low voltage v il 0.8 v logic-input high voltage v ih 2.0 v input leakage current i lkg -1 +1 ? output low voltage v ol i sink = 3ma 0.4 v input/output capacitance c i/o 10 pf serial interface timing characteristics (figure 3) (in1 = gnd, v in2 ? in7 = 2.7v to 5.5v, v in8 = 10v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1, 2, 3) parameter sym b o l conditions min typ max units serial clock frequency f scl 400 khz clock low period t low 1.3 ? clock high period t high 0.6 ? bus-free time t buf 1.3 ? start setup time t su:sta 0.6 ? start hold time t hd:sta 0.6 ? stop setup time t su:sto 0.6 ? data in setup time t su:dat 100 ns data in hold time t hd:dat 30 900 ns receive scl/sda minimum rise time t r (note 5) 20 + 0.1 x c bus ns receive scl/sda maximum rise time t r (note 5) 300 ns receive scl/sda minimum fall time t f (note 5) 20 + 0.1 x c bus ns receive scl/sda maximum fall time t f (note 5) 300 ns transmit sda fall time t f c bus = 400pf 20 + 0.04 x c bus 300 ns
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 6 _______________________________________________________________________________________ note 1: 100% production tested at t a = +25? and t a = +85?. specifications at t a = -40? are guaranteed by design. note 2: specifications are guaranteed for the stated global conditions. the device also meets the parameters specified when 0 < v in1 < 6.5v and at least one of v in2 ? in5 is between 2.7v and 5.5v, while the remaining v in2 ? in5 are between 0 and 5.5v. specifications are also guaranteed if v cc is externally supplied. note 3: device may be supplied from any one of in1 to in5, or v cc (see the powering the max6889/max6890/max6891 section). note 4: the internal supply voltage, measured at v cc , equals the maximum of in2 to in5 if v in1 = 0v, or equals 5.4v if v in1 > 6.5v. for 4v < v in1 < 6.5v and v in2 ? in5 > 2.7v, the input that powers the device cannot be determined. note 5: c bus = total capacitance of one bus line in pf. rise and fall times are measured between 0.1 x v bus and 0.9 x v bus . note 6: input filters on sda, scl, a0, and a1 suppress noise spikes < 50ns. note 7: an additional cycle is required when writing to configuration memory for the first time. typical operating characteristics (v in1 = 6.5v to 13.2v, v in8 = 10v, v in_ = 2.7v to 5.5v, gpi_ = gnd, margin = mr = dbp, t a = +25?, unless otherwise noted.) supply current vs. supply voltage (in1) max6889 toc01 supply voltage (v) supply current (ma) 12.5 11.5 10.5 9.5 8.5 7.5 0.8 0.9 1.0 1.1 1.2 1.3 0.7 6.5 13.5 t a = +85 c t a = -40 c t a = +25 c 5.0 4.5 4.0 3.5 3.0 2.5 5.5 supply current vs. supply voltage (in2?n5) max6889 toc02 supply voltage (v) supply current (ma) 0.7 0.8 0.9 1.0 1.1 1.2 0.6 t a = +85 c t a = -40 c t a = +25 c normalized po_ timeout period vs. temperature max6889 toc03 temperature ( c) normalized po_ timeout period 60 35 10 -15 0.8 0.9 1.0 1.1 1.2 1.3 0.7 -40 85 serial interface timing characteristics (figure 3) (continued) (in1 = gnd, v in2 ? in7 = 2.7v to 5.5v, v in8 = 10v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1, 2, 3) parameter sym b o l conditions min typ max units pulse width of spike suppressed t sp (note 6) 50 ns eeprom byte write cycle time t wr (note 7) 11 ms
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 7 in_ to po_ propagation delay ( s) 12 14 16 18 20 22 24 26 28 30 10 in_ to po_ propagation delay vs. temperature max6889 toc04 temperature ( c) 60 35 10 -15 -40 85 100mv overdrive normalized watchdog timeout period 0.985 0.990 0.995 1.000 1.010 1.005 1.015 1.020 0.980 normalized watchdog timeout period vs. temperature max6889 toc05 temperature ( c) 60 35 10 -15 -40 85 normalized in_ threshold 0.998 0.997 0.996 0.999 1.000 1.001 1.003 1.002 1.004 1.005 0.995 normalized in_ threshold vs. temperature max6889 toc06 temperature ( c) 60 35 10 -15 -40 85 100 10 1 1000 maximum in_ transient vs. in_ threshold overdrive max6889 toc07 in_ threshold overdrive (mv) maximum transient duration ( s) 25 50 75 100 125 150 175 200 0 po_ assertion occurs above this line output voltage low vs. sink current max6889 toc08 i sink (ma) v ol (mv) 13 14 12 10 11 3456789 12 50 100 150 200 250 300 350 400 450 500 0 015 0.24 0.20 0.12 0.16 0.08 0.04 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 0 0 output voltage high vs. source current max6889 toc09 i out (ma) v oh (mv) weak pullup mr to po_ propagation delay ( s) 1.85 1.90 1.95 2.00 2.10 2.05 2.15 2.20 1.80 mr to po_ propagation delay vs. temperature max6889 toc10 temperature ( c) 60 35 10 -15 -40 85 typical operating characteristics (continued) (v in1 = 6.5v to 13.2v, v in8 = 10v, v in_ = 2.7v to 5.5v, gpi_ = gnd, margin = mr = dbp, t a = +25?, unless otherwise noted.)
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 8 _______________________________________________________________________________________ pin description pin max6889 max6890 max6891 name function 111po2 programmable output 2. configurable, active-high, active-low, open-drain, or weak pullup output. po2 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po2 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 222po3 programmable output 3. configurable, active-high, active-low, open-drain, or weak pullup output. po3 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po3 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 333po4 programmable output 4. configurable, active-high, active-low, open-drain, or weak pullup output. po4 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po4 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 4 4 4 gnd ground 555po5 programmable output 5. configurable, active-high, active-low, open-drain, or weak pullup output. po5 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po5 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 6 6 po6 programmable output 6. configurable, active-high, active-low, open-drain, or weak pullup output. po6 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po6 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 7 7 po7 programmable output 7. configurable, active-high, active-low, open-drain, or weak pullup output. po7 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po7 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 8 8 po8 programmable output 8. configurable, active-high, active-low, open-drain, or weak pullup output. po8 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po8 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 9 po9 programmable output 9. configurable, active-high, active-low, open-drain, or weak pullup output. po9 pulls low with a 10? internal current sink for +1v < v cc < v uvlo . po9 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 10 po10 programmable output 10. configurable, active-high, active-low, open-drain, or weak pullup output. po10 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po10 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. 11 9 6 margin margin input. margin holds po_ in its existing state when margin is driven low. leave margin unconnected or connect to dbp if unused. margin overrides mr if both assert at the same time. margin is internally pulled up to dbp through a 10? current source.
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 9 pin description (continued) pin max6889 max6890 max6891 name function 12 10 7 mr manual reset input. mr is configurable to either assert po_ into a programmed state or to have no effect on po_ when driving mr low (see table 6). leave mr unconnected or connect to dbp if unused. mr is internally pulled up to dbp through a 10? current source. 13 11 8 sda serial data input/output (open drain). sda requires an external pullup resistor. 14 12 9 scl serial clock input. scl requires an external pullup resistor. 15 13 10 a0 address input 0. address inputs allow up to four (max6889/max6890) or two (max6891) connections on one common bus. connect a0 to gnd or to the serial-interface power supply. 16 14 a1 address input 1. address inputs allow up to four max6889/max6890 connections on one common bus. connect a1 to gnd or to the serial-interface power supply. 17 15 gpi4 general-purpose logic input 4. an internal 10? current source pulls gpi4 to gnd. configure gpi4 to control watchdog timer functions or the programmable outputs. 18 16 11 gpi3 general-purpose logic input 3. an internal 10? current source pulls gpi3 to gnd. configure gpi3 to control watchdog timer functions or the programmable outputs. 19 17 12 gpi2 general-purpose logic input 2. an internal 10? current source pulls gpi2 to gnd. configure gpi2 to control watchdog timer functions or the programmable outputs. 20 18 13 gpi1 general-purpose logic input 1. an internal 10? current source pulls gpi1 to gnd. configure gpi1 to control watchdog timer functions or the programmable outputs. 21 19 14 v cc internal power-supply voltage. bypass v cc to gnd with a 1? ceramic capacitor. v cc supplies power to the internal circuitry. v cc is internally powered from the highest of the monitored in1?n5 voltages. do not use v cc to supply power to external circuitry. to externally supply v cc , see the powering the max6889/max6890/max6891 section. 22 20 15 dbp internal digital power-supply voltage. bypass dbp to gnd with a 1? ceramic capacitor. dbp supplies power to the eeprom memory, the internal logic circuitry, and the programmable outputs. do not use dbp to supply power to external circuitry. 23 in8 high-voltage input 8. configure in8 to detect voltage thresholds from 2.5v to 15.25v in 50mv increments, or 1.25v to 7.625v in 25mv increments. for improved noise immunity, bypass in8 to gnd with a 0.1? capacitor installed as close to the device as possible. 24 in7 voltage input 7. configure in7 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in7 to gnd with a 0.1? capacitor installed as close to the device as possible.
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 10 ______________________________________________________________________________________ pin description (continued) pin max6889 max6890 max6891 name function 25 21 in6 voltage input 6. configure in6 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in6 to gnd with a 0.1? capacitor installed as close to the device as possible. 26 22 in5 voltage input 5. configure in5 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in5 to gnd with a 0.1? capacitor installed as close to the device as possible. 27 23 16 in4 voltage input 4. configure in4 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in4 to gnd with a 0.1? capacitor installed as close to the device as possible. 28 24 17 in3 voltage input 3. configure in3 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in3 to gnd with a 0.1? capacitor installed as close to the device as possible. 29 25 18 in2 voltage input 2. configure in2 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in2 to gnd with a 0.1? capacitor installed as close to the device as possible. 30 26 19 in1 high-voltage input 1. configure in1 to detect voltage thresholds from 2.5v to 13.2v in 50mv increments, or 1.25v to 7.625v in 25mv increments. for improved noise immunity, bypass in1 to gnd with a 0.1? capacitor installed as close to the device as possible. 31 27 n.c. no connection. not internally connected. 32 28 20 po1 programmable output 1. configurable, active-high, active-low, open-drain, or weak pullup output. po1 pulls low with a 10? internal current sink for 1v < v cc < v uvlo . po1 assumes its programmed conditional output state when v cc exceeds undervoltage lockout (uvlo) of 2.5v. ep ep ep gnd exposed paddle. internally connected to gnd. connect exposed paddle to gnd or leave floating.
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 11 programmable array gpi1 gpi2 gpi3 gpi4 * margin mr timing block 1 timing block 2 timing block 3 timing block 4 timing block 5 timing block 6 timing block 7 timing block 8 timing block 9 timing block 10 main oscillator v ref in2 detector in3 detector in4 detector in5 detector in6 detector in2 in3 in4 in5* in6* in1 in_ detector po2 output po3 output po4 output po5 output po6 output po7 output po8 output po2 po3 po4 po5 po6* po7* po8* po1 1 f 1 f 2-wire interface sda scl a0 a1 user eeprom config registers config eeprom gnd * for max6889/max6890 only. ** for max6889 only. in7 detector in7** in8 detector in8** 5.4v ldo po9 output po10 output po9** po10** open-drain or weak pullup switch 2.55v ldo output 10k ? po_ output 10 a power-up pulldown lo/ hi eeprom charge pump 2.55v ldo dbp v cc max6889 max6890 max6891 virtual diodes functional diagram
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 12 ______________________________________________________________________________________ detailed description the max6889/max6890/max6891 eeprom-config- urable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and general- purpose logic inputs, and feature programmable out- puts for highly-configurable power-supply sequencing applications. the max6889 features eight voltage detector inputs and ten programmable outputs. the max6890 features six voltage detector inputs and eight programmable outputs, while the max6891 features four voltage detector inputs and five programmable outputs. manual reset and margin disable inputs simpli- fy board-level testing during the manufacturing process. all voltage detectors provide configurable thresholds for undervoltage detection. the high-voltage input (in1) monitors voltages from 1.25v to 7.625v in 25mv incre- ments, or 2.5v to 13.2v in 50mv increments. inputs (in2?n7) monitor voltages from 0.5v to 3.05v in 10mv increments, or 1.0v to 5.5v in 20mv increments. an additional high-voltage input (in8, max6889 only) mon- itors voltages from 1.25v to 7.625v in 25mv incre- ments, or 2.5v to 15.25v in 50mv increments. to monitor thresholds from 0.1667v to 1.0167v in 3.3mv increments, the respective input voltage detector must be programmed for high impedance (high-z) and an external voltage-divider must be connected. the host controller communicates with the max6889/max6890/max6891s?internal 512-bit user eeprom, configuration eeprom, and configuration registers through an smbus/i 2 c-compatible serial inter- face (see figure 1). programmable output options include active-high, active- low, open drain, and weak pullup. program each output to assert on any voltage detector input, general-purpose logic input, watchdog timer, or manual reset. program- mable timing delay blocks configure each output to wait between 25? and 1600ms before deasserting. the max6889/max6890/max6891 feature a watchdog timer for added flexibility. program the watchdog timer to assert one or more programmable outputs. program the watchdog timer to clear on a combination of one gpi_ input and one programmable output, one of the gpi_ inputs only, or one of the programmable outputs only. the initial and normal watchdog timeout periods are independently programmable from 6.25ms to 102.4s. logic network for po_ comparators mr, gpi_, margin in _ output stages analog block digital block serial interface register bank boot controller eeprom (user and config) sda, scl watchdog timer gpi_ po_ figure 1. top-level block diagram
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 13 powering the max6889/max6890/max6891 the max6889/max6890/max6891 derive power from the voltage detector inputs: in1?n5 (max6889/ max6890), in1?n4 (max6891), or an external v cc supply. a virtual diode-oring scheme selects the posi- tive input that supplies power to the device (see the functional diagram ). in1 must be at least 4v, or one of in2?n5 (max6889/max6890)/in2?n4 (max6891) must be at least 2.7v to ensure device operation. an internal ldo regulates in1 down to 5.4v. the highest input voltage on in2?n5 (max6889/ max6890)/in2?n4 (max6891) supplies power to the device, unless v in1 > 6.5v, in which case in1 supplies power to the device. for 4v < v in1 < 6.5v and one of v in2 ? in5 > 2.7v, the input power source cannot be determined due to the dropout voltage of the ldo. internal hysteresis ensures that the supply input that ini- tially powered the device continues to power the device when multiple input voltages are within 50mv of each other. v cc powers the analog circuitry. bypass v cc to gnd with a 1? ceramic capacitor installed as close to the device as possible. the internal supply voltage, mea- sured at v cc , equals the maximum of in2?n5 if v in1 = 0v, or equals 5.4v when v in1 > 6.5v. do not use the internally generated v cc to provide power to external circuitry. power cannot be supplied through high- impedance voltage detector inputs. to externally sup- ply power through v cc : max6889/max6890/max6891 feature description high-voltage input in1 2.5v to 13.2v threshold in 50mv increments. 1.25v to 7.625v threshold in 25mv increments. positive voltage input in2?n7 (max6889) in2?n6 (max6890) in2?n4 (max6891) 1v to 5.5v threshold in 20mv increments. 0.5v to 3.05v threshold in 10mv increments. 0.1667v to 1.0167v threshold in 3.3mv increments in high-z mode. high-voltage input in8 (max6889) 2.5v to 15.25v threshold in 50mv increments. 1.25v to 7.625v threshold in 25mv increments. 0.1667v to 1.0167v threshold in 3.3mv increments in high-z mode. programmable outputs po1?o10 (max6889) po1?o8 (max6890) po1?o5 (max6891) active-high or active-low. open-drain or weak pullup output. dependent on mr , margin , in_, gpi_, and wd. programmable reset timeout periods of 25?, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms, or 1.6s. general-purpose logic inputs: gpi1?pi4 (max6889?ax6890) gpi1?pi3 (max6891) active-high or active-low logic levels. configure gpi_ as inputs to the watchdog timer or the programmable output stages. watchdog timer clear dependent on any combination of one gpi_ input and one programmable output, a gpi_ input only, or a programmable output only. initial watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s. normal watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s. watchdog enable/disable. manual reset input ( mr ) forces po_ into the active output state when mr = gnd. po_ deassert after mr releases high and the po_ timeout period expires. v cc power mode programs whether the device is powered from the highest in_ input or from an external supply connected to v cc . write disable locks user eeprom based on po_. configuration lock locks configuration registers and eeprom. table 1. programmable features
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 14 ______________________________________________________________________________________ 1) apply a voltage between 2.7v and 5.5v to one of v cc or in2?n5. 2) program the internal/external v cc power eeprom at aeh, bit[2] = 1 (see table 22). 3) power down the device. subsequent power-ups and software reboots require an externally supplied v cc to ensure the device is fully operational. the max6889/max6890/max6891 also generate a dig- ital supply voltage (dbp) for the internal logic circuitry and the eeprom. bypass dbp to gnd with a 1? ceramic capacitor installed as close to the device as possible. the nominal dbp output voltage is 2.55v. do not use dbp to provide power to external circuitry. inputs the max6889/max6890/max6891 contain multiple logic and voltage detector inputs. each voltage detec- tor input is monitored for undervoltage thresholds. table 1 summarizes these various inputs. set the threshold voltage for each voltage detector input with registers 00h?7h. each threshold voltage is an under- voltage threshold. set the threshold range for each volt- age detector with register 08h. high-voltage input (in1) in1 offers threshold voltages of 2.5v to 13.2v in 50mv increments, or 1.25v to 7.625v in 25mv increments. use the following equations to set the threshold volt- ages for in1: where v th is the desired threshold voltage and x is the decimal code for the desired threshold (table 2). for the 2.5v to 13.2v range, x must equal 214 or less; oth- erwise the threshold exceeds the maximum operating voltage of in1. in2?n7 the in2?n7 positive voltage detectors monitor volt- ages from 1v to 5.5v in 20mv increments, 0.5v to 3.05v in 10mv increments, or 0.1667v to 1.0167v in 3.3mv increments in high-z mode. use the following equations to set the threshold voltages for in_: where v th is the desired threshold voltage and x is the decimal code for the desired threshold (table 3). for the 1v to 5.5v range, x must equal 225 or less; other- wise the threshold exceeds the maximum operating voltage of in2?n7. high-voltage input (in8) configure in8 to detect positive thresholds from 2.5v to 15.25v in 50mv increments, 1.25v to 7.625v in 25mv increments, or 0.1667v to 1.0167v in 3.3mv increments in high-z mode. use the following equations to set the threshold voltages for in8: where v th is the desired threshold voltage and x is the decimal code for the desired threshold (table 4). x vv v for v to v range x vv v for v to v range x vv v for v to v high z range th th th = = = ? ? ? ? 25 005 2 5 15 25 125 0 025 1 25 7 625 0 1667 0 0033 0 1667 1 0167 . . .. . . .. . . .. x vv v for v to v range x vv v for v to v range x vv v for v to v high z range th th th = = = ? ? ? ? 1 002 155 05 01 05 305 0 1667 0 0033 0 1667 1 0167 . . . . .. . . .. x vv v for v to v range x vv v for v to v range th th = ? = ? 25 005 2 5 13 2 125 0 025 1 25 7 625 . . .. . . .. register address eeprom memory address bit range description 00h 80h [7:0] in1 undervoltage detector threshold (v1) (see equations in the inputs section) 08h 88h [0] in1 range selection. 0 = 2.5v to 13.2v range in 50mv increments. 1 = 1.25v to 7.625v range in 25mv increments. 09h 89h [0] must be set to ??for normal operation table 2. in1 threshold settings
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 15 gpi1?pi4 the gpi1?pi4 (general-purpose input) programmable logic inputs control power-supply sequencing (pro- grammable outputs), reset/interrupt signaling, and watchdog functions (see the configuring the watchdog timer section). configure gpi1?pi4 for active-low or active-high logic (table 5). gpi1?pi4 internally pull down to gnd through a 10? current sink. mr the manual reset ( mr ) input initiates a reset condition. see table 6 to program the po_ outputs to assert when mr is low. all affected programmable outputs remain asserted (see the programmable outputs section) for their po_ timeout periods after mr releases high. an internal 10? current source pulls mr to dbp. leave mr unconnected or connect to dbp if unused. max6889/max6890/max6891 register address eeprom memory address bit range description 01h 81h [7:0] in2 undervoltage detector threshold (v2) (see equations in the inputs section) 02h 82h [7:0] in3 undervoltage detector threshold (v3) (see equations in the inputs section) 03h 83h [7:0] in4 undervoltage detector threshold (v4) (see equations in the inputs section) 04h 84h [7:0] in 5 ( m ax 6889/m ax 6890 onl y) und er voltag e d etector thr eshol d ( v 5) ( see equations i n the inputs secti on) 05h 85h [7:0] in 6 ( m ax 6889/m ax 6890 onl y) und er voltag e d etector thr eshol d ( v 6) ( see equations i n the inputs secti on) 06h 86h [7:0] in7 (max6889 only) undervoltage detector threshold (v7) (see equations in the inputs section) [1] in2 range selection, 0 = 1v to 5.5v range in 20mv increments, 1 = 0.5v to 3.05v range in 10mv increments [2] in3 range selection, 0 = 1v to 5.5v range in 20mv increments, 1 = 0.5v to 3.05v range in 10mv increments [3] in4 range selection, 0 = 1v to 5.5v range in 20mv increments, 1 = 0.5v to 3.05v range in 10mv increments [4] in5 (max6889/max6890 only) range selection, 0 = 1v to 5.5v range in 20mv increments, 1 = 0.5v to 3.05v range in 10mv increments [5] in6 (max6889/max6890 only) range selection, 0 = 1v to 5.5v range in 20mv increments, 1 = 0.5v to 3.05v range in 10mv increments [6] in7 (max6889 only) range selection, 0 = 1v to 5.5v range in 20mv increments, 1 = 0.5v to 3.05v range in 10mv increments 08h 88h [7] not used [1] in2 input impedance. 0 = normal mode. 1 = high-z mode, with a 0.1667v to 1.0167v range in 3.3mv increments. [2] in3 input impedance. 0 = normal mode. 1 = high-z mode, with a 0.1667v to 1.0167v range in 3.3mv increments. [3] in4 input impedance. 0 = normal mode. 1 = high-z mode, with a 0.1667v to 1.0167v range in 3.3mv increments. [4] in5 input impedance. 0 = normal mode. 1 = high-z mode, with a 0.1667v to 1.0167v range in 3.3mv increments. [5] in6 input impedance. 0 = normal mode. 1 = high-z mode, with a 0.1667v to 1.0167v range in 3.3mv increments. 09h 89h [6] in7 input impedance. 0 = normal mode. 1 = high-z mode, with a 0.1667v to 1.0167v range in 3.3mv increments. table 3. in2Cin7 threshold settings
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 16 ______________________________________________________________________________________ margin margin allows system-level testing while power sup- plies exceed the normal ranges. driving margin low forces the programmable outputs to hold the last state while system-level testing occurs. leave margin unconnected or connect to dbp if unused. an internal 10? current source pulls margin to dbp. the state of each programmable output does not change while margin = gnd. margin overrides mr if both assert at the same time. programmable outputs the max6889 features ten programmable outputs, the max6890 features eight programmable outputs, and the max6891 features five programmable outputs. selectable output stage configurations include: active- low or active-high, open drain, or weak pullup. during power-up, the programmable outputs pull to gnd with an internal 10? current sink for 1v < v cc < v uvlo . the programmable outputs remain in their active states until their respective po timeout period expires, and all of the programmed conditions are met for each output. any output programmed to depend on no condition always remains in its active state (table 17). an output configured as active-high is considered asserted when that output is logic-high. the voltage monitors generate fault signals (logical 0) to the max6889/max6890/max6891s?logic array when an input voltage is below the programmed undervoltage threshold. for example, the po3 (table 9) programmable output may depend on the in1 undervoltage threshold, and the state of gpi1. write ?? to r10h[0] and r11h[1] to configure as indicated. in1 must be above the under- voltage threshold (table 2) and gpi1 must be inactive (table 5) to be a logic ?,?then po3 deasserts. the logic state of po3, in this example, is equivalent to the logical statement: ?1 gpi1. registers 0ah through 27h configure each of the pro- grammable outputs. programmable timing blocks set the po_ timeout period from 25? to 1600ms for each programmable output. see table 17 to set the active state (active-high or active-low) for each programmable output and tables 18 and 19 to select the output stage types, and po_ timeout periods for each output. each programmable output allows a different set of condi- tions to assert each output as shown in tables 7?6. register address eeprom memory address bit range description 07h 87h [7:0] in8 undervoltage detector threshold (v8) (see equations in the inputs section) 08h 88h [7] in8 range selection. 0 = 2.5v to 15.25v range in 50mv increments. 1 = 1.25v to 7.625v range in 25mv increments. 09h 89h [7] in8 input impedance. 0 = normal mode. 1 = high-z mode, with a 0.1667v to 1.0167v range in 3.3mv increments. table 4. in8 threshold settings register address eeprom address bit range description [0] gpi1. 0 = active-low, 1 = active-high. [1] gpi2. 0 = active-low, 1 = active-high. [2] gpi3. 0 = active-low, 1 = active-high. 28h a8h [3] gpi4 (max6889/max6890 only). 0 = active-low, 1 = active-high. table 5. gpi1Cgpi4 active logic states
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 17 max6889/max6890/max6891 register address eeprom memory address bit range description 0bh 8bh [5] po1. 0 = po1 independent of mr , 1 = po1 asserts when mr = low. 0eh 8eh [5] po2. 0 = po2 independent of mr , 1 = po2 asserts when mr = low. 11h 91h [5] po3. 0 = po3 independent of mr , 1 = po3 asserts when mr = low. 14h 94h [5] po4. 0 = po4/po2 independent of mr , 1 = po4 asserts when mr = low. 17h 97h [5] po5. 0 = po5 independent of mr , 1 = po5 asserts when mr = low. 1ah 9ah [5] po6 (max6889/max6890 only). 0 = po6 independent of mr , 1 = po6 asserts when mr = low. 1dh 9dh [5] po7 (max6889/max6890 only). 0 = po7 independent of mr , 1 = po7 asserts when mr = low. 20h a0h [5] po8 (max6889/max6890 only). 0 = po8 independent of mr , 1 = po8 asserts when mr = low. 23h a3h [5] po9 (max6889 only). 0 = po9 independent of mr , 1 = po9 asserts when mr = low. 26h a6h [5] po10 (max6889 only). 0 = po10 independent of mr , 1 = po10 asserts when mr = low. table 6. programmable output behavior and mr register address eeprom memory address bit output assertion conditions [0] 1 = po1 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po1 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po1 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po1 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po1 assertion depends on in5 (max6889/max6890 only) undervoltage threshold (table 3) [5] 1 = po1 assertion depends on in6 (max6889/max6890 only) undervoltage threshold (table 3) [6] 1 = po1 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 0ah 8ah [7] 1 = po1 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po1 assertion depends on watchdog (table 20) [1] 1 = po1 assertion depends on gpi1 (table 5) [2] 1 = po1 assertion depends on gpi2 (table 5) [3] 1 = po1 assertion depends on gpi3 (table 5) [4] 1 = po1 assertion depends on gpi4 (max6889/max6890 only) (table 5) [5] 1 = po1 asserts when mr = low (table 6) 0bh 8bh [7:6] not used table 7. po1 output dependency note: table 7 only applies to po1. write a ??to a bit to make the po1 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ).
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 18 ______________________________________________________________________________________ register address eeprom memory address bit output assertion conditions [0] 1 = po2 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po2 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po2 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po2 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po2 assertion depends on in5 (max6889/max6890 only) undervoltage threshold (table 3) [5] 1 = po2 assertion depends on in6 (max6889/max6890 only) undervoltage threshold (table 3) [6] 1 = po2 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 0dh 8dh [7] 1 = po2 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po2 assertion depends on watchdog (table 20) [1] 1 = po2 assertion depends on gpi1 (table 5) [2] 1 = po2 assertion depends on gpi2 (table 5) [3] 1 = po2 assertion depends on gpi3 (table 5) [4] 1 = po2 assertion depends on gpi4 (max6889/max6890 only) (table 5) [5] 1 = po2 asserts when mr = low (table 6) 0eh 8eh [7:6] not used table 8. po2 output dependency note: table 8 only applies to po2. write a ??to a bit to make the po2 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ).
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 19 register address eeprom memory address bit output assertion conditions [0] 1 = po3 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po3 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po3 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po3 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po3 assertion depends on in5 (max6889/max6890 only) undervoltage threshold (table 3) [5] 1 = po3 assertion depends on in6 (max6889/max6890 only) undervoltage threshold (table 3) [6] 1 = po3 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 10h 90h [7] 1 = po3 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po3 assertion depends on watchdog (table 20) [1] 1 = po3 assertion depends on gpi1 (table 5) [2] 1 = po3 assertion depends on gpi2 (table 5) [3] 1 = po3 assertion depends on gpi3 (table 5) [4] 1 = po3 assertion depends on gpi4 (max6889/max6890 only) (table 5) [5] 1 = po3 asserts when mr = low (table 6) 11h 11h [7:6] not used table 9. po3 output dependency note: table 9 only applies to po3. write a ??to a bit to make the po3 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ).
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 20 ______________________________________________________________________________________ register address eeprom memory address bit output assertion conditions [0] 1 = po4 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po4 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po4 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po4 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po4 assertion depends on in5 (max6889/max6890 only) undervoltage threshold (table 3) [5] 1 = po4 assertion depends on in6 (max6889/max6890 only) undervoltage threshold (table 3) [6] 1 = po4 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 13h 93h [7] 1 = po4 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po4 assertion depends on watchdog (table 20) [1] 1 = po4 assertion depends on gpi1 (table 5) [2] 1 = po4 assertion depends on gpi2 (table 5) [3] 1 = po4 assertion depends on gpi3 (table 5) [4] 1 = po4 assertion depends on gpi4 (max6889/max6890 only) (table 5) [5] 1 = po4 asserts when mr = low (table 6) 14h 14h [7:6] not used table 10. po4 output dependency note: table 10 only applies to po4. write a ??to a bit to make the po4 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ).
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 21 register address eeprom memory address bit output assertion conditions [0] 1 = po5 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po5 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po5 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po5 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po5 assertion depends on in5 (max6889/max6890 only) undervoltage threshold (table 3) [5] 1 = po5 assertion depends on in6 (max6889/max6890 only) undervoltage threshold (table 3) [6] 1 = po5 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 16h 96h [7] 1 = po5 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po5 assertion depends on watchdog (table 20) [1] 1 = po5 assertion depends on gpi1 (table 5) [2] 1 = po5 assertion depends on gpi2 (table 5) [3] 1 = po5 assertion depends on gpi3 (table 5) [4] 1 = po5 assertion depends on gpi4 (max6889/max6890 only) (table 5) [5] 1 = po5 asserts when mr = low (table 6) 17h 17h [7:6] not used table 11. po5 output dependency note: table 11 only applies to po5. write a ??to a bit to make the po5 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ).
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 22 ______________________________________________________________________________________ register address eeprom memory address bit output assertion conditions [0] 1 = po7 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po7 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po7 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po7 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po7 assertion depends on in5 undervoltage threshold (table 3) [5] 1 = po7 assertion depends on in6 undervoltage threshold (table 3) [6] 1 = po7 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 1ch 9ch [7] 1 = po7 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po7 assertion depends on watchdog (table 20) [1] 1 = po7 assertion depends on gpi1 (table 5) [2] 1 = po7 assertion depends on gpi2 (table 5) [3] 1 = po7 assertion depends on gpi3 (table 5) [4] 1 = po7 assertion depends on gpi4 (table 5) [5] 1 = po7 asserts when mr = low (table 6) 1dh 9dh [7:6] not used table 13. po7 (max6889/max6890 only) output dependency note: table 13 only applies to po7 (max6889/max6890 only). write a ??to a bit to make the po7 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ). register address eeprom memory address bit output assertion conditions [0] 1 = po6 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po6 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po6 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po6 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po6 assertion depends on in5 undervoltage threshold (table 3) [5] 1 = po6 assertion depends on in6 undervoltage threshold (table 3) [6] 1 = po6 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 19h 99h [7] 1 = po6 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po6 assertion depends on watchdog (table 20) [1] 1 = po6 assertion depends on gpi1 (table 5) [2] 1 = po6 assertion depends on gpi2 (table 5) [3] 1 = po6 assertion depends on gpi3 (table 5) [4] 1 = po6 assertion depends on gpi4 (table 5) [5] 1 = po4 asserts when mr = low (table 6) 1ah 9ah [7:6] not used table 12. po6 (max6889/max6890 only) output dependency note: table 12 only applies to po6 (max6889/max6890 only). write a ??to a bit to make the po6 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ).
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 23 register address eeprom memory address bit output assertion conditions [0] 1 = po9 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po9 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po9 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po9 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po9 assertion depends on in5 undervoltage threshold (table 3) [5] 1 = po9 assertion depends on in6 undervoltage threshold (table 3) [6] 1 = po9 assertion depends on in7 undervoltage threshold (table 3) 22h a2h [7] 1 = po9 assertion depends on in8 undervoltage threshold (table 4) [0] 1 = po9 assertion depends on watchdog (table 20) [1] 1 = po9 assertion depends on gpi1 (table 5) [2] 1 = po9 assertion depends on gpi2 (table 5) [3] 1 = po9 assertion depends on gpi3 (table 5) [4] 1 = po9 assertion depends on gpi4 (table 5) [5] 1 = po9 asserts when mr = low (table 6) 23h a3h [7:6] not used table 15. po9 (max6889 only) output dependency note: table 15 only applies to po9 (max6889 only). write a ??to a bit to make the po9 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ). register address eeprom memory address bit output assertion conditions [0] 1 = po8 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po8 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po8 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po8 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po8 assertion depends on in5 undervoltage threshold (table 3) [5] 1 = po8 assertion depends on in6 undervoltage threshold (table 3) [6] 1 = po8 assertion depends on in7 (max6890 only) undervoltage threshold (table 3) 1fh 9fh [7] 1 = po8 assertion depends on in8 (max6890 only) undervoltage threshold (table 4) [0] 1 = po8 assertion depends on watchdog (table 20) [1] 1 = po8 assertion depends on gpi1 (table 5) [2] 1 = po8 assertion depends on gpi2 (table 5) [3] 1 = po8 assertion depends on gpi3 (table 5) [4] 1 = po8 assertion depends on gpi4 (table 5) [5] 1 = po8 asserts when mr = low (table 6) 20h a0h [7:6] not used table 14. po8 (max6889/max6890 only) output dependency note: table 14 only applies to po8 (max6889/max6890 only). write a ??to a bit to make the po8 output independent of the respective signal (in_ thresholds, wd, gpi_, or mr ).
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 24 ______________________________________________________________________________________ register address eeprom memory address bit output assertion conditions [0] 1 = po10 assertion depends on in1 undervoltage threshold (table 2) [1] 1 = po10 assertion depends on in2 undervoltage threshold (table 3) [2] 1 = po10 assertion depends on in3 undervoltage threshold (table 3) [3] 1 = po10 assertion depends on in4 undervoltage threshold (table 3) [4] 1 = po10 assertion depends on in5 undervoltage threshold (table 3) [5] 1 = po10 assertion depends on in6 undervoltage threshold (table 3) [6] 1 = po10 assertion depends on in7 undervoltage threshold (table 3) 25h a5h [7] 1 = po10 assertion depends on in8 undervoltage threshold (table 4) [0] 1 = po10 assertion depends on watchdog (table 20) [1] 1 = po10 assertion depends on gpi1 (table 5) [2] 1 = po10 assertion depends on gpi2 (table 5) [3] 1 = po10 assertion depends on gpi3 (table 5) [4] 1 = po10 assertion depends on gpi4 (table 5) [5] 1 = po10 asserts when mr = low (table 6) 26h a6h [7:6] not used table 16. po10 (max6889 only) output dependency note: table 16 only applies to po10 (max6890 only). write a ??to a bit to make the po10 output independent of the respective sig- nal (in_ thresholds, wd, gpi_, or mr ). register address eeprom memory address bit range affected output description 0ch 8ch [1] po1 0 = active-low, 1 = active-high 0fh 8fh [1] po2 0 = active-low, 1 = active-high 12h 92h [1] po3 0 = active-low, 1 = active-high 15h 95h [1] po4 0 = active-low, 1 = active-high 18h 98h [1] po5 0 = active-low, 1 = active-high 1bh 9bh [1] po6 max6889/max6890 only. 0 = active-low, 1 = active-high. 1eh 9eh [1] po7 max6889/max6890 only. 0 = active-low, 1 = active-high. 21h a1h [1] po8 max6889/max6890 only. 0 = active-low, 1 = active-high. 24h a4h [1] po9 max6889 only. 0 = active-low, 1 = active-high. 27h a7h [1] po10 max6889 only. 0 = active-low, 1 = active-high. table 17. programmable output active states
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 25 output stage configurations independently configure each programmable output as active-high or active-low (table 17). additionally, config- ure each programmable output as open drain or weak pullup (table 18). finally, set the po_ timeout period for each programmable output (table 19). the programma- ble outputs can sink up to 4ma. weak pullup output configuration the max6889/max6890/max6891s?programmable outputs have a pullup resistance (10k ? , typ) connected to the inter- nal 2.55v ldo output to provide weak pullup outputs. open-drain output configuration connect an external pullup resistor from the program- mable output to an external voltage when configured as an open-drain output. open-drain configured outputs may be pulled up to 13.2v. choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consump- tion. the open-drain output configuration allows wire- ored connections, and provides flexibility in setting the pullup current. configuring the watchdog timer (registers 29h?ah) a watchdog timer monitors microprocessor software execution for a stalled condition and resets the micro- processor if it stalls. the output of the watchdog timer (one of the programmable outputs) connects to the reset input or a nonmaskable interrupt of the microprocessor. registers 29h?ah configure the watchdog functionali- ty of the max6889/max6890/max6891. program the watchdog timer to assert one or more programmable outputs (see tables 7?6). program the watchdog timer to reset on one of the gpi_ inputs, one of the program- mable outputs, or a combination of one gpi_ input and one programmable output. the watchdog timer features independent initial and normal watchdog timeout periods. the initial watchdog timeout period applies immediately after power-up, after a software reboot, after a reset event takes place, or after enabling the watchdog timer. the initial watch- dog timeout period allows the microprocessor to per- form its initialization process. if no pulse occurs during the initial watchdog timeout period, the microprocessor is taking too long to initialize, indicating a potential problem. the normal watchdog timeout period applies after the initial watchdog timeout period occurs. the normal watchdog timeout period monitors a pulsed output of the microprocessor that indicates when normal proces- sor behavior occurs. if no pulse occurs during the nor- mal watchdog timeout period, this indicates that the processor has stopped operating or is stuck in an infi- nite execution loop. register 2ah programs the initial and normal watchdog timeout periods, and enables or disables the watchdog timer. see tables 20 and 21 for a summary of the watchdog behavior. configuration lock lock the configuration register bank and configuration eeprom contents after initial programming by setting the lock bit high (see table 22). locking the configura- tion prevents write operations to all registers except the configuration lock register. clear the lock bit to reconfig- ure the device. internal/external v cc power the max6889/max6890/max6891 can generate an internal v cc , or v cc can be externally supplied (see table 22). to internally generate v cc from the highest voltage on in1?n5 set register 2eh and eeprom address aeh bit[2] = 0. to use an externally supplied, always-on v cc ensure register 2eh and eeprom address aeh bit[2] =1 (see the powering the max6889/ max6890/max6891 section). write disable a unique write-disable feature protects the max6889/ max6890/max6891 from inadvertent user-eeprom writes. as input voltages that power the serial interface, a microprocessor, or any other writing-devices fall, unintentional data may be written onto the data bus. the user-eeprom write-disable function (see table 23) ensures that unintentional data does not corrupt the max6889/max6890/max6891 eeprom data.
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 26 ______________________________________________________________________________________ register address eeprom memory address bit range affected output description 0ch 8ch [0] po1 0 = weak pullup, 1 = open drain 0fh 8fh [0] po2 0 = weak pullup, 1 = open drain 12h 92h [0] po3 0 = weak pullup, 1 = open drain 15h 95h [0] po4 0 = weak pullup, 1 = open drain 18h 98h [0] po5 0 = weak pullup, 1 = open drain 1bh 9bh [0] po6 max6889/max6890 only. 0 = weak pullup, 1 = open drain. 1eh 9eh [0] po7 max6889/max6890 only. 0 = weak pullup, 1 = open drain. 21h a1h [0] po8 max6889/max6890 only. 0 = weak pullup, 1 = open drain. 24h a4h [0] po9 max6889 only. 0 = weak pullup, 1 = open drain. 27h a7h [0] po10 max6889 only. 0 = weak pullup, 1 = open drain. table 18. programmable output stage options register address eeprom memory address bit range affected outputs description 0ch 8ch [4:2] po1 0fh 8fh [4:2] po2 12h 92h [4:2] po3 15h 95h [4:2] po4 18h 98h [4:2] po5 1bh 9bh [4:2] po6 (max6889/max6890) 1eh 9eh [4:2] po7 (max6889/max6890) 21h a1h [4:2] po8 (max6889/max6890) 24h a4h [4:2] po9 (max6889 only) 27h a7h [4:2] po10 (max6889 only) 000 = 25? 001 = 1.5625ms 010 = 6.25ms 011 = 25ms 100 = 50ms 101 = 200ms 110 = 400ms 111 = 1600ms table 19. po_ timeout periods
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 27 register address eeprom memory address bit range description [1:0] watchdog input selection: 00 = gpi1 input 01 = gpi2 input 10 = gpi3 input 11 = gpi4 input (max6889/max6890 only). selects gpi3 on max6891. [5:2] watchdog internal input selection: 0000 = po1 0001 = po2 0010 = po3 0011 = po4 0100 = po5 0101 = po6 (max6889/max6890 only) 0110 = po7 (max6889/max6890 only) 0111 = po8 (max6889/max6890 only) 1000 = po9 (max6889 only) 1001 = po10 (max6889 only) [1011] to [1111] = wd is not affected by po_ 29h a9h [7:6] watchdog dependency on inputs: 00 = watchdog not dependent on any input 01 = watchdog clear depends on selected gpi_ input only 01 = watchdog clear depends on selected po_ input only 11 = watchdog clear depends on both selected gpi_ and po_ inputs table 20. watchdog inputs
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 28 ______________________________________________________________________________________ register address eeprom memory address bit range description [2:0] normal watchdog timeout period: 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s [5:3] initial watchdog timeout period (immediately following power-up, reset event, or enabling watchdog): 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s [6] watchdog enable 0 = disables watchdog timer 1 = enables watchdog timer 2ah aah [7] not used table 21. watchdog timeout period selection register address eeprom memory address bit range description [0] 0 = configuration unlocked 1 = configuration locked [1] not used [2] internal/external v cc power: 0 = v cc internally generated 1 = v cc externally supplied 2eh aeh [7:3] not used table 22. configuration lock and internal/external v cc power register
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 29 register address eeprom memory address bit range description [0] 0 = write is not disabled if po1 asserts 1 = write disabled if po1 asserts [1] 0 = write is not disabled if po2 asserts 1 = write disabled if po2 asserts [2] 0 = write is not disabled if po3 asserts 1 = write disabled if po3 asserts [3] 0 = write is not disabled if po4 asserts 1 = write disabled if po4 asserts [4] 0 = write is not disabled if po5 asserts 1 = write disabled if po5 asserts [5] 0 = write is not disabled if po6 asserts 1 = write disabled if po6 asserts [6] 0 = write is not disabled if po7 asserts 1 = write disabled if po7 asserts 2ch ach [7] 0 = write is not disabled if po8 asserts 1 = write disabled if po8 asserts [0] 0 = write is not disabled if po9 asserts 1 = write disabled if po9 asserts [1] 0 = write is not disabled if po10 asserts 1 = write disabled if po10 asserts 2dh adh [7:2] not used table 23. write disable register configuring the max6889/max6890/max6891 the max6889/max6890/max6891 factory-default con- figuration sets all registers to 0h, except bits in tables 17 and 18, which are set to 1h. factory-default configu- ration sets all po_? as active-high, open drain (all out- puts are high impedance until the device is configured by the user). each device requires configuration before full power is applied to the system. to configure the max6889/max6890/max6891, first apply an input volt- age to in1, or one of in2?n5 or v cc (see the powering the max6889/max6890/max6891 section). v in1 > 4v, or one of v in2 ? in5 or v cc > 2.7v to ensure device operation. next, transmit data through the serial inter- face. use the block write protocol to quickly configure the device. write to the configuration registers first to ensure the device is configured properly. after com- pleting the setup procedure, use the read word or block read protocol to read back the data from the con- figuration registers. lastly, use the write byte or block write protocol to write this data to the eeprom regis- ters. after completing the eeprom register configura- tion, apply full power to the system to begin normal operation. the nonvolatile eeprom stores the latest configuration upon removal of power. write 0s to all eeprom registers to clear the memory. software reboot a software reboot allows the user to restore the eeprom configuration to the volatile registers without cycling the power supplies. use the send byte command with data byte c4h to initiate a software reboot. the 3ms (max) power-up delay also applies after a software reboot. configuration eeprom the configuration eeprom addresses range from 80h to aeh. write data to the configuration eeprom to auto- matically set up the max6889/max6890/max6891 upon power-up. data is transferred from the configuration eeprom to the configuration registers when v cc exceeds uvlo during power-up or after a software
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 30 ______________________________________________________________________________________ stop condition repeated start condition start condition t high t low t r t f t su:dat t su:sta t su:sto t hd:sta t buf t hd:sta t hd:dat scl sda start condition figure 3. serial-interface timing details reboot. after v cc exceeds uvlo, an internal 1mhz clock starts after a 5? delay, and data transfer begins. data transfer disables access to the configuration regis- ters and eeprom. the data transfer from eeprom to configuration registers takes 3ms (max). read configu- ration eeprom data at any time after power-up or soft- ware reboot. write commands to the configuration eeprom are allowed at any time after power-up or soft- ware reboot, unless the configuration lock bit is set (see table 22). the maximum cycle time to write a single byte is 11ms (max). user eeprom the 512-bit, user-eeprom addresses range from 40h to 7fh (see figure 2). store software revision data, board revision data, and other data in these registers. the max- imum cycle time to write a single byte is 11ms (max). configuration register bank and eeprom the configuration registers can be directly modified through the serial interface without modifying the eeprom, after the power-up procedure terminates and the configuration eeprom data has been loaded into the configuration register bank. use the write byte or block write protocols to write directly to the configuration regis- ters. changes to the configuration registers take effect immediately and are lost upon power removal. at device power-up, the register bank loads configura- tion data from the eeprom. configuration data may be directly altered in the register bank during application development, allowing maximum flexibility. transfer the new configuration data byte-by-byte to the configura- tion eeprom with the write byte protocol. the next device power-up or software reboot automatically loads the new configuration. smbus/i 2 c-compatible serial interface the max6889/max6890/max6891 feature an i 2 c/smbus- compatible 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the max6889/max6890/max6891 and the master device at clock rates up to 400khz. figure 3 shows the 2-wire inter- face timing diagram. the max6889/max6890/max6891 are transmit/receive slave-only devices, relying upon a 40h user eeprom 7fh 80h configuration eeprom aeh 00h register bank 37h reserved figure 2. memory map
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 31 max6889/max6890/max6891 max6889/max6890/max6891 max6889/max6890/max6891 master device to generate a clock signal. the master device (typically a microcontroller) generates scl and ini- tiates data transfer on the bus. a master device communicates to the max6889/ max6890/max6891 by transmitting the proper address followed by command and/or data words. each trans- mit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. scl is a logic input, while sda is an open-drain input/output. scl and sda both require external pullup resistors to generate the logic-high voltage. use 4.7k ? resistors for most applications. bit transfer each clock pulse transfers one data bit. the data on sda must remain stable while scl is high (figure 4), otherwise the max6889/max6890/max6891 register a start or stop condition (figure 5) from the master. sda and scl idle high when the bus is not busy. start and stop conditions a master device signals the beginning of a transmission with a start (s) condition (figure 5) by transitioning sda from high to low while scl is high. the master device issues a stop (p) condition (figure 5) by transi- tioning sda from low to high while scl is high. a stop condition frees the bus for another transmission. the bus remains active if a repeated start condition is gener- ated, such as in the read byte or block read protocol (see figure 8). both scl and sda are high when the bus is not busy. early stop conditions the max6889/max6890/max6891 recognize a stop condition at any point during transmission except if a stop condition occurs in the same high pulse as a start condition. this condition is not a legal i 2 c for- mat. at least one clock pulse must separate any start and stop condition. repeated start conditions a repeated start (sr) condition may indicate a change of data direction on the bus. such a change occurs when a command word is required to initiate a read operation (see figure 8). sr may also be used when the bus master is writing to several i 2 c devices and does not want to relinquish control of the bus. the max6889/max6890/max6891 serial interface supports continuous write operations with or without an sr condi- tion separating them. continuous read operations require sr conditions because of the change in direction of data flow. acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. the receiving device always generates an ack. the max6889/max6890/max6891 generate an ack when receiving an address or data by pulling sda low during the 9th clock period (figure 6). when trans- mitting data, such as when the master device reads data back from the max6889/max6890/max6891, the max6889/max6890/max6891 wait for the master device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if the receiving device is busy or if a sys- tem fault has occurred. in the event of an unsuccessful data line stable, data valid sda scl change of data allowed figure 4. bit transfer p s start condition sda scl stop condition figure 5. start and stop conditions
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 32 ______________________________________________________________________________________ data transfer, the bus master should reattempt communi- cation at a later time. the max6889/max6890/ max6891 generate a nack after the command byte during a software reboot, while writing to the eeprom, or when receiving an illegal memory address. slave address sa7 through sa4 represent the standard 2-wire inter- face address (1010) for devices with eeprom. sa3 and sa2 correspond to the a1 and a0 address inputs of the max6889/max6890/max6891 (hardwired as logic-low or logic-high). sa0 is a read/write flag bit (0 = write, 1 = read). the a0 and a1 address inputs allow up to four max6889/max6890 to connect to one bus, while the a0 address input allows up to two max6891s to con- nect to one bus. connect a0 and a1 to gnd or to the 2-wire serial-interface power supply (see figure 7). scl 1 s 2 89 sda by transmitter sda by receiver start condition clock pulse for acknowledge figure 6. acknowledge sda scl 1 msb lsb start 01 0 a1 a0 xr/w ack figure 7. slave address the max6889/max6890 slave address conforms to the following table: x = don? care sa7 (msb) sa6 sa5 sa4 sa3 sa2 sa1 sa0 (lsb) 1 0 1 0 a1 a0 x r/ w the max6891 slave address conforms to the following table: x = don? care sa7 (msb) sa6 sa5 sa4 sa3 sa2 sa1 sa0 (lsb) 1 0100a0x r/ w
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 33 send byte the send byte protocol allows the master device to send one byte of data to the slave device (see figure 8). the send byte presets a register pointer address for a subsequent read or write. the slave sends a nack instead of an ack if the master tries to send an address that is not allowed or if the device is writing data to eeprom or is booting. if the master sends c0h, the data is ack. this could be the start of the block write protocol, and the slave expects the following data bytes. if the master sends a stop condition, the internal address pointer does not change. if the master sends c1h, this signifies that the block read protocol is expected, and a repeated start condition should follow. the device reboots if the master sends c4h. the send byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit data byte. 5) the addressed slave asserts an ack on sda. 6) the master sends a stop condition. write byte the write byte protocol allows the master device to write a single byte in the register bank or in the eeprom (configuration or user) (see figure 8). the write byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit command code. 5) the addressed slave asserts an ack on sda. 6) the master sends an 8-bit data byte. 7) the addressed slave asserts an ack on sda. 8) the master sends a stop condition. in order to write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. the command code must be in the range of 00h to 2eh. the data byte is written to the register bank if the command code is valid. the slave generates a nack at step 5 if the command code is invalid or any internal operations are ongoing. in order to write a single byte of data to the user or con- figuration eeprom, the 8-bit command code and a sin- gle 8-bit data byte are sent. the following 8-bit data byte is written to the addressed eeprom location. block write the block write protocol allows the master device to write a block of data (1 to 16 bytes) to the eeprom or to the register bank (see figure 8). the destination address must already be set by the send byte protocol and the command code must be c0h. if the number of bytes to be written causes the address pointer to exceed 2fh for the configuration register or b7h for the configuration eeprom, the address pointer stops incrementing, overwriting the last memory address with the remaining bytes of data. only the last data byte sent is stored in b7h (as 2fh is read only and a write causes no change in the content). if the number of bytes to be written exceeds the address pointer 7fh for the user eeprom, the address pointer stops incre- menting and continues writing exceeding data to the last address. only the last data is actually written to 7fh. the block write procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends the 8-bit command code for block write (c0h). 5) the addressed slave asserts an ack on sda. 6) the master sends the 8-bit byte count (1 to 16 bytes) n. 7) the addressed slave asserts an ack on sda. 8) the master sends 8 bits of data. 9) the addressed slave asserts an ack on sda. 10) repeat steps 8 and 9 n ?1 times. 11) the master generates a stop condition.
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 34 ______________________________________________________________________________________ read byte the read byte protocol allows the master device to read the register or an eeprom location (user or con- figuration) content of the max6889/max6890/max6891 (see figure 8). the read byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends 8 data bits. 5) the active slave asserts an ack on the data line. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave id plus a read bit (high). 8) the addressed slave asserts an ack on the data line. 9) the slave sends 8 data bits. 10) the master asserts a nack on the data line 11) the master generates a stop condition. note that once the read has been done, the internal pointer is increased by one, unless a memory boundary is hit. if the device is busy or if the address is not an allowed one, the command code is nacked and the internal address pointer is not altered. the master must then interrupt the communication issuing a stop condition. block read the block read protocol allows the master device to read a block of 16 bytes from the eeprom or register bank (see figure 8). read fewer than 16 bytes of data by issu- ing an early stop condition from the master, or by gen- erating a nack with the master. previous actions through the serial interface predetermines the first source address. it is suggested to use a send byte protocol, before the block read, to set the initial read address. the block read protocol is initiated with a command code of c1h. the block read procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends 8 bits of the block read com- mand (c1h). 5) the slave asserts an ack on sda, unless busy. 6) the master generates a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the slave asserts an ack on sda. 9) the slave sends the 8-bit byte count (16). 10) the master asserts an ack on sda. 11) the slave sends 8 bits of data. 12) the master asserts an ack on sda. 13) repeat steps 8 and 9 15 times. 14) the master generates a stop condition. address pointers use the send byte protocol to set the register address pointers before read and write operations. for the con- figuration registers, valid address pointers range from 00h to 2fh. register addresses outside of this range result in a nack being issued from the max6889/ max6890/max6891. when using the block write proto- col, the address pointer automatically increments after each data byte, except when the address pointer is already at 2fh. if the address pointer is already 2fh, and more data bytes are being sent, these subsequent bytes overwrite address 2fh repeatedly. no data will be left in 2fh as this is a read-only address. for the configuration eeprom, valid address pointers range from 80h to b7h (even if they are only meaningful up to aeh). when using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at b7h. if the address pointer is already b7h, and more data bytes are being sent, these subsequent bytes overwrite address b7h repeatedly, leaving only the last sent data byte stored at this register address. for the user eeprom, valid address pointers range from 40h to 7fh. as for the configuration eeprom, block write and block read protocols can also be used. the internal address pointer will auto-increment up to the user-eeprom boundary 7fh where the pointer will stop incrementing. when writing, only the last data writ- ten will be stored in 7fh.
max6889/max6890/max6891 max6889/max6890/max6891 max6889/max6890/max6891 max6889/max6890/max6891 max6889/max6890/max6891 max6889/max6890/max6891 max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 35 write byte format s address 7 bits send byte format wr ack data 8 bits ack p data byte?resets the internal address pointer or represents a command. block write format s address wr ack command ack byte count= n ack data byte 1 ack data byte ... ack data byte n ack p 7 bits c0h 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte prepares device for block write operation. data byte?irst data goes into the address preset with a previous "set address" and the following data in the following locations. block read format s address wr ack command ack sr address wr ack 8 bits byte count = n ack data byte 1 ack data byte ... ack data byte n ack p 7 bits c1h 7 bits 8 bits 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte prepares device for block operation. slave address equivalent to chip- select line of a 3- wire interface. data byte?ata comes from the address set by a previous "send byte". s = start condition. p = stop condition. shaded = slave transmission. sr = repeated start condition. slave address equivalent to chip- select line of a 3- wire interface. s address wr ack command ack data ack p 7 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte selects register eeprom location you are writing to. data byte?ata goes into the register (or eeprom location) set by the command byte. 0 0 0 1 0 read byte format s address wr ack data ack sr ack data ack p 7 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3-wire interface. data byte?resets the internal address pointer. data byte?ata read from the preset register (or eeprom) address. 0 address wr 7 bits 1 slave address equivalent to chip- select line of a 3-wire interface. figure 8. smbus/i 2 c protocols applications information configuration download at power-up the configuration of the max6889/max6890/max6891 (undervoltage thresholds, po_ timeout periods, watch- dog behavior, programmable output conditions and configurations, etc.) depends on the contents of the eeprom. the eeprom is comprised of buffered latch- es that store the configuration. the local volatile memo- ry latches lose their contents at power-down. therefore, at power-up, the device configuration must be restored by downloading the contents of the eeprom (non- volatile memory) to the local latches. this download occurs in a number of steps: 1) programmable outputs go high impedance with no power applied to the device. 2) when v cc exceeds 1v, all programmable outputs are weakly pulled to gnd through a 10? current sink. 3) when v cc exceeds uvlo, the configuration eeprom starts to download its contents to the volatile configuration registers. the programmable outputs assume their programmed conditional out- put state when v cc exceeds uvlo.
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 36 ______________________________________________________________________________________ register address eeprom memory address read/ write description 00h 80h r/w in1 undervoltage detector threshold (table 2) 01h 81h r/w in2 undervoltage detector threshold (table 3) 02h 82h r/w in3 undervoltage detector threshold (table 3) 03h 83h r/w in4 undervoltage detector threshold (table 3) 04h 84h r/w in5 undervoltage detector threshold (max6889/max6890 only) (table 3) 05h 85h r/w in6 undervoltage detector threshold (max6889/max6890 only) (table 3) 06h 86h r/w in7 undervoltage detector threshold (max6889 only) (table 3) 07h 87h r/w in8 undervoltage detector threshold (max6889 only) (table 4) 08h 88h r/w threshold range selection (tables 2, 3, and 4) 09h 89h r/w high-z mode selection (tables 2, 3, and 4) 0ah 8ah r/w po1 input selection (table 7) 0bh 8bh r/w po1 input selection (table 7) 0ch 8ch r/w po1 timeout period, programmable output polarity, and output type selection (tables 17, 18, and 19) 0dh 8dh r/w po2 input selection (table 8) 0eh 8eh r/w po2 input selection (table 8) register map 4) any attempt to communicate with the device prior to this download completion results in a nack being issued from the max6889/max6890/max6891. forcing programmable outputs high during power-up a weak, 10? pulldown current holds all programmable outputs low during power-up until v cc exceeds the undervoltage-lockout (uvlo) threshold. applications requiring a guaranteed high programmable output for v cc down to gnd require external pullup resistors to maintain the logic state until v cc exceeds uvlo. use 20k ? resistors for most applications. uses for general-purpose inputs (gpi_) watchdog timer program gpi_ as an input to the watchdog timer in the max6889/max6890/max6891. the gpi_ input must toggle within the watchdog timeout period; otherwise any programmable output dependent on the watchdog timer will assert. additional manual reset functions the programmable outputs allow a set of conditions to assert the output. program the set of conditions to depend on one of the gpi_ inputs. any output that depends on gpi_ asserts when gpi_ is held in its active state, effectively acting as a manual reset input. other fault signals from ? connect a general-purpose output from a ? to one of the gpi_ inputs to allow interrupts to assert any output of the max6889/max6890/max6891. configure one of the programmable outputs to assert on whichever gpi_ input connects to the general-purpose output of the ?. layout and bypassing for better noise immunity, bypass each of the voltage detector inputs to gnd with 0.1? capacitors installed as close to the device as possible. bypass v cc and dbp to gnd with 1? capacitors installed as close to the device as possible. v cc (when not externally supplied) and dbp are internally generated voltages and should not be used to supply power to external circuitry. configuration latency period a delay of less than 5? occurs between writing to the configuration registers and the time when these changes actually take place, unless when changing one of the voltage detector? thresholds. changing a voltage detector threshold typically takes 150?. when changing eeprom contents, a software reboot or cycling of power is required for these changes to trans- fer to volatile memory. chip information process: bicmos
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 37 register address eeprom memory address read/ write description 0fh 8fh r/w po2 timeout period and output type selection (tables 17, 18, and 19) 10h 90h r/w po3 input selection (table 9) 11h 91h r/w po3 input selection (table 9) 12h 92h r/w po3 timeout period and output type selection (tables 17, 18, and 19) 13h 93h r/w po4 input selection (table 10) 14h 94h r/w po4 input selection (table 10) 15h 95h r/w po4 timeout period and output type selection (tables 17, 18, and 19) 16h 96h r/w po5 input selection (table 11) 17h 97h r/w po5 input selection (table 11) 18h 98h r/w po5 timeout period and output type selection (tables 17, 18, and 19) 19h 99h r/w po6 (max6889/max6890) input selection (table 12) 1ah 9ah r/w po6 (max6889/max6890) input selection (table 12) 1bh 9bh r/w p o6 ( m ax 6889/m ax 6890) ti m eout p er i od and outp ut typ e sel ecti on ( tab l es 17, 18, and 19) 1ch 9ch r/w po7 (max6889/max6890) input selection (table 13) 1dh 9dh r/w po7 (max6889/max6890) input selection (table 13) 1eh 9eh r/w p o7 ( m ax 6889/m ax 6890) ti m eout p er i od and outp ut typ e sel ecti on ( tab l es 17, 18, and 19) 1fh 9fh r/w po8 (max6889/max6890) input selection (table 14) 20h a0h r/w po8 (max6889/max6890) input selection (table 14) 21h a1h r/w p o8 ( m ax 6889/m ax 6890) ti m eout p er i od and outp ut typ e sel ecti on ( tab l es 17, 18, and 19) 22h a2h r/w po9 (max6889 only) input selection (table 15) 23h a3h r/w po9 (max6889 only) input selection (table 15) 24h a4h r/w po9 (max6889 only) timeout period and output type selection (tables 17, 18, and 19) 25h a5h r/w po10 (max6889 only) input selection (table 16) 26h a6h r/w po10 (max6889 only) input selection (table 16) 27h a7h r/w po10 (max6889 only) timeout period and output type selection (tables 17, 18, and 19) 28h a8h r/w gpi_ input polarity selection 29h a9h r/w wd input selection and clear dependency (table 20) 2ah aah r/w wd initial and normal timeout duration and disable (table 21) 2bh abh reserved. should not be overwritten. 2ch ach r/w user eeprom write disable (table 23) 2dh adh r/w user eeprom write disable (table 23) 2eh aeh r/w configuration lock and internal/external v cc power (table 22) register map (continued)
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors 38 ______________________________________________________________________________________ 32 31 30 29 28 27 26 9 101112131415 18 19 20 21 22 23 24 7 6 5 4 3 2 1 max6889 (5mm x 5mm thin qfn) top view po3 po2 po4 gnd po5 po6 po7 8 *exposed pad *exposed pad internally connected to gnd. po8 po1 n.c. in1 in2 in3 in4 in5 25 in6 in7 in8 dbp v cc gpi1 gpi2 gpi3 17 gpi4 a0 scl 16 a1 sda mr margin po10 po9 28 27 26 25 24 23 22 8 9 10 11 12 13 16 17 18 19 20 21 7 6 5 4 3 2 1 (5mm x 5mm thin qfn) top view po3 po2 po4 gnd po5 po6 po7 *exposed pad *exposed pad internally connected to gnd. po1 n.c. in1 in2 in3 in4 in5 in6 dbp v cc gpi1 gpi2 gpi3 15 gpi4 a0 scl 14 a1 sda mr margin po8 20 19 18 17 16 678910 11 12 13 14 15 5 4 3 2 1 (5mm x 5mm thin qfn) top view po3 po2 po4 gnd po5 *exposed pad *exposed pad internally connected to gnd. po1 in1 in2 in3 in4 dbp v cc gpi1 gpi2 gpi3 a0 scl sda mr margin max6890 max6891 pin configurations
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 39 max6891 dc-dc 1 dbp po1 in1 dc-dc 2 in2 po2 dc-dc 3 in3 po3 gnd in4 sda sda 2.5v 3.3v 5v 12v p scl scl po4 reset po5 a0 nmi, wd alert gpi1 (wd) logic output r pu r pu 12v supply po1 po2 po3 12v bus input t po1 enable 5v dc-dc converter gpi2 gpi3 v cc margin mr 12v 5v supply 5v output t po2 enable 2.5v dc-dc converter 2.5v supply 2.5v output t po3 enable 3.3v dc-dc converter 3.3v supply po4 3.3v output system reset t po4 typical operating circuit package type package code document no. 20 tqfn t2055-5 21-0140 28 tqfn t2855-8 21-0140 32 tqfn t3255-4 21-0140 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
max6889/max6890/max6891 eeprom-programmable, octal/hex/quad, power-supply sequencers/supervisors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 40 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/05 initial release 1 9/08 added specifications to electrical characteristics .4

▲Up To Search▲

Price & Availability of MAX6889ETJ

	To Download MAX6889ETJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .